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| Dual-Channel Ultralow Noise Amplifier with Selectable Gain and Input Impedance AD8432 FEATURES Low noise Input voltage noise: 0.85 nV/Hz Current noise: 2.0 pA/Hz Excellent ac specifications 200 MHz bandwidth (G = 12.04 dB) 295 V/s slew rate Selectable gain G = 12.04 dB (x4) G = 18.06 dB (x8) G = 21.58 dB (x12) G = 24.08 dB (x16) Active input impedance matching Integrated input clamp diodes Single-ended input, differential output Supply range: 4.5 V to 5.5 V Low power: 60 mW/channel FUNCTIONAL BLOCK DIAGRAM ENB VPS1 VPS2 COMM BIAS AD8432 INH1 IND1 LNA1 OPL1 GMH1 GOH1 GOL1 GML1 OPH2 IND2 LNA2 OPL2 GMH2 GOH2 GOL2 GML2 OPH1 INL1 INH2 Figure 1. APPLICATIONS CW Doppler ultrasound front ends Low noise preamplification Predriver for I/Q demodulators and phase shifters Wideband analog-to-digital drivers GENERAL DESCRIPTION The AD8432 is a dual-channel, low power, ultralow noise amplifier with selectable gain and active impedance matching. Each amplifier has a single-ended input, differential output, and integrated input clamps. By pin strapping the gain setting pins, four accurate gains of G = 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (x4, x8, x12, and x16) are possible. A bandwidth of 200 MHz at G = 12.04 dB makes this amplifier well suited for many high speed applications. The exceptional noise performance of the AD8432 is made possible by the active impedance matching. Using a feedback network, the input impedance of the amplifiers can be adjusted to match the signal source impedance without compromising the noise performance. Impedance matching and low noise of the AD8432 allow designers to create wider dynamic range systems that are able to detect even very low level signals. The AD8432 achieves 0.85 nV/Hz input referred voltage noise for a gain of 12.04 dB. The AD8432's ultralow noise, low distortion, excellent gain accuracy, and channel-to-channel matching are ideal for high performance ultrasound systems and for processing I/Q demodulator signals. The AD8432 operates on a single supply of 5 V at 24 mA. It is available in a 4 mm x 4 mm, 24-lead LFSCP. The LFCSP features an exposed paddle that provides a low thermal resistance path to the PCB, which enables more efficient heat transfer and increases reliability. The operating temperature range is -40C to +85C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. 08341-001 INL2 AD8432 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Test Circuits ..................................................................................... 16 Theory of Operation ...................................................................... 18 Low Noise Amplifier (LNA) ..................................................... 18 Gain Setting Technique ............................................................. 18 Active Input Resistance Matching............................................ 19 Applications Information .............................................................. 21 Typical Setup ............................................................................... 21 I/Q Demodulation Front End ................................................... 23 Differential-to-Single-Ended Conversion............................... 24 Evaluation Board ............................................................................ 25 Gain Setting................................................................................. 25 Power Supply............................................................................... 27 Input Termination ...................................................................... 27 Output .......................................................................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 10/09--Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD8432 SPECIFICATIONS VS = 5 V, TA = 25C, RS = RIN = 50 , RFB =150 , CSH = 47 pF, RSH = 15 , RL = 500 (per SE output), CL = 5 pF (per SE output), G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified. Table 1. Parameter DYNAMIC PERFORMANCE Gain Range Gain Error -3 dB Small Signal Bandwidth Conditions Input to differential output (selectable gain) Input to single output (selectable gain) RIN unterminated, RFB = , CSH = 0 pF, RSH = 0 G = 12.04 dB G = 18.06 dB G = 21.58 dB G = 24.08 dB VOUT = 2 V p-p VOUT = 2 V p-p, f = 10 MHz VOUT = 2 V p-p, f = 10 MHz Min 12.04 6.02 0.1 200 90 50 32 42 295 170 10 0.85 2.0 2.8 4.8 4.2 3.2 2.1 2.3 3.4 6.8 10.2 13.6 -67 -74 -103 -106 -65 -72 -103 -92 -66 -62 -78 -73 -60 -56 -72 -65 Typ Max 24.08 18.06 1 Unit dB dB dB MHz MHz MHz MHz MHz V/s V/s ns nV/Hz pA/Hz dB dB dB dB dB dB nV/Hz nV/Hz nV/Hz nV/Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc -3 dB Large Signal Bandwidth Slew Rate (Rising Edge) Slew Rate (Falling Edge) Overdrive Recovery Time DISTORTION/NOISE PERFORMANCE Input Voltage Noise Input Current Noise Noise Figure Unterminated Active Termination RFB = RFB = RS = 50 , RFB = RS = RIN = 50 , RFB = 150 RS = 50 , RFB = 226 , RIN = 75 RS = 50 , RFB = 301 , RIN = 100 RS = 50 , RFB = 619 , RIN = 200 RS = 50 , RFB = 3.57 k, RIN = 1 k G = 12.04 dB, RFB = G = 18.06 dB, RFB = G = 21.58 dB, RFB = G = 24.08 dB, RFB = HD2 HD2, RS = 50 , RIN unterminated HD3 HD3, RS = 50 , RIN unterminated HD2 HD2, RS = 50 , RIN unterminated HD3 HD3, RS = 50 , RIN unterminated HD2 HD2, RS = 50 , RIN unterminated HD3 HD3, RS = 50 , RIN unterminated HD2 HD2, RS = 50 , RIN unterminated HD3 HD3, RS = 50 , RIN unterminated Output Referred Noise Harmonic Distortion 1 MHz (VOUT = 1 V p-p) 1 MHz (VOUT = 2 V p-p) 10 MHz (VOUT = 1 V p-p) 10 MHz (VOUT = 2 V p-p) Rev. 0 | Page 3 of 28 AD8432 Parameter Two-Tone IMD3 Distortion 10 MHz 1 MHz Input 1dB Compression Point Output Third-Order Intercept 1 MHz 10 MHz 1 MHz 10 MHz Crosstalk DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift INPUT CHARACTERISTICS Input Voltage Range Input Resistance Conditions RS = 50 , RIN unterminated VOUT = 1 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz VOUT = 2 V p-p, f1 = 9.5 MHz, f2 = 10.5 MHz VOUT = 1 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz VOUT = 2 V p-p, f1 = 0.9 MHz, f2 = 1.1 MHz f = 1 MHz f = 10 MHz VOUT = 1 V p-p of composite tones VOUT = 2 V p-p of composite tones VOUT = 1 V p-p of composite tones VOUT = 2 V p-p of composite tones VOUT = 1 V p-p of composite tones, reference to 50 VOUT = 2 V p-p of composite tones, reference to 50 VOUT = 1 V p-p of composite tones, reference to 50 VOUT = 2 V p-p of composite tones, reference to 50 VOUT = 1 V p-p, f = 1 MHz -6.25 Min Typ -89.1 -66.0 -88.9 -73.7 7.5 7.7 29.7 28.2 23.2 24.2 42.7 41.2 36.2 37.2 102 +1 300 1.2 50 75 100 200 1 6.2 6 3.25 2.5 +4 4.8 <0.1 2.5 77 200 200 5 24 21 27 50 120 -82 +6.25 Max Unit dBc dBc dBc dBc dBm dBm dBV rms dBV rms dBV rms dBV rms dBm dBm dBm dBm dB mV V/C V p-p k k pF V V mV V p-p k mA s s V mA mA mA A mW dB AC-coupled RFB = 150 RFB = 226 RFB = 301 RFB = 619 RFB = 3.57 k RFB = , f = 100 kHz Input Capacitance Input Common Mode Voltage OUTPUT CHARACTERISTCS Output Common-Mode Voltage Output Offset Voltage Output Voltage Swing Output Resistance Output Resistance in Shutdown Mode Output Short-Circuit Current Enable Response Time POWER SUPPLY Supply Voltage Quiescent Current Over Temperature Supply Current in Shutdown Mode Power Dissipation PSRR -25 Single-ended, either output Single-ended, either output RL = 10 differential ENBON (enable high to output on) ENBOFF (enable low to output off ) 4.5 All channels enabled TA = -40C TA = +85C ENB = GND G = 24.08 dB, f = 100 kHz, no bypass capacitors +25 5.5 100 Rev. 0 | Page 4 of 28 AD8432 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage Supply Voltage Input Voltage Power Dissipation Temperature Operating Temperature Storage Temperature Package Glass Transition Temperature (TG) Lead Temperature (Soldering, 60 sec) Rating 5.5 V 0 V to VPS 120 mW -40C to +85C -65C to +150C 150C 300C MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the AD8432 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 150C for an extended period can cause changes in silicon devices, potentially resulting in a loss of functionality. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. The JA values in Table 3 assume a 4-layer JEDEC standard board with zero airflow. Table 3. Thermal Resistance1 Parameter 40-Lead LFCSP 1 JA 57.9 JC 11.2 JB 35.9 JT 1.1 Unit C/W 4-Layer JEDEC board (2S2P). Rev. 0 | Page 5 of 28 AD8432 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 GMH1 21 GOH1 19 GML1 24 ENB 23 VPS1 22 OPH1 INH1 1 INL1 2 IND1 3 COMM 4 INL2 5 INH2 6 9 GOH2 10 GMH2 11 GML2 12 VPS2 8 IND2 7 18 GOL1 17 OPL1 AD8432 TOP VIEW (Not to Scale) 16 COM1 15 COM2 14 OPL2 13 GOL2 OPH2 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3, 7 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic INH1 INL1 IND1, IND2 COMM INL2 INH2 VPS2 OPH2 GOH2 GMH2 GML2 GOL2 OPL2 COM2 COM1 OPL1 GOL1 GML1 GMH1 GOH1 OPH1 VPS1 ENB EPAD Description LNA1 Noninverting Input. LNA1 Inverting Input (AC-Coupled to Ground). Integrated Input Clamping Back-to-Back Diodes. Input Ground. LNA2 Inverting Input (AC-Coupled to Ground). LNA2 Noninverting Input. 5 V Supply for LNA2. Noninverting Output of LNA2. Gain Setting Pin for LNA2. Gain Setting Pin for LNA2. Gain Setting Pin for LNA2. Gain Setting Pin for LNA2. Inverting Output of LNA2. LNA2 Output Ground. LNA1 Output Ground. Inverting Output of LNA1. Gain Setting Pin for LNA1. Gain Setting Pin for LNA1. Gain Setting Pin for LNA1. Gain Setting Pin for LNA1. Noninverting Output of LNA1. 5 V Supply of LNA1 . Enable. Exposed pad must be connected to ground. Rev. 0 | Page 6 of 28 08341-002 AD8432 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, RS = RIN = 50 , RFB =150 , CSH = 47 pF, RSH = 15 , RL =500 (per SE output), CL = 5 pF (per SE output), G = 12.04 dB (single-ended input to differential output), f = 1 MHz, unless otherwise specified. 30 24 24 18 18 12 15 GAIN (dB) G G G G 1 GAIN (dB) 6 0 -6 -12 -18 -24 -30 10 100 1k FREQUENCY (MHz) 12 9 6 = 24.08dB = 21.58dB = 18.06dB = 12.04dB 08341-003 3 0 1 RIN UNTERMINATED RIN = 200 RIN = 100 RIN = 50 10 FREQUENCY (MHz) 100 500 08341-006 Figure 3. Small Signal Differential Gain vs. Frequency, RIN Unterminated 24 21 18 15 12 GAIN (dB) 9 6 3 0 -3 -6 -9 -12 1 GAIN (dB) Figure 6. Small Signal Frequency Response vs. RIN, G = 21.58 dB 27 24 21 18 15 12 9 6 RIN UNTERMINATED RIN = 200 RIN = 100 RIN = 50 08341-004 3 10 100 500 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response vs. RIN, G = 12.04 dB 24 21 Figure 7. Small Signal Frequency Response vs. RIN, G = 24.08 dB 27 G = 24.08dB 24 G = 21.58dB 21 18 15 G = 18.06dB 18 15 GAIN (dB) GAIN (dB) 12 9 6 3 G = 12.04dB 12 9 6 3 0 1 RIN UNTERMINATED RIN = 200 RIN = 100 RIN = 50 08341-005 0 -3 -6 100 500 10 FREQUENCY (MHz) 1 10 FREQUENCY (MHz) 100 500 Figure 5. Small Signal Frequency Response vs. RIN, G = 18.06 dB Figure 8. Differential Gain vs. Frequency, VOUT = 1 V p-p, RIN = 50 Rev. 0 | Page 7 of 28 08341-010 -9 08341-007 0 RIN UNTERMINATED RIN = 200 RIN = 100 RIN = 50 AD8432 30 24 18 12 INPUT IMPEDANCE () G G G G 1 = 24.08dB = 21.58dB = 18.06dB = 12.04dB 08341-011 240 230 220 210 200 190 180 170 160 0.1 GAIN (dB) 6 0 -6 -12 -18 -24 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB 1 FREQUENCY (MHz) 10 08341-031 08341-033 10 100 1k FREQUENCY (MHz) Figure 9. Differential Gain vs. Frequency, VOUT = 2 V p-p , RIN = 50 55 54 53 52 51 50 49 48 47 46 45 0.1 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB 08341-029 Figure 12. Input Impedance RIN vs. Frequency, 200 Active Termination 10 INPUT IMPEDANCE (k) INPUT IMPEDANCE () 1 1 FREQUENCY (MHz) 10 1 FREQUENCY (MHz) 10 Figure 10. Input Impedance RIN vs. Frequency, 50 Active Termination 115 Figure 13. Input Impedance RIN vs. Frequency, Unterminated 3.5 3.0 OUTPUT IMPEDANCE () 110 INPUT IMPEDANCE () 2.5 2.0 1.5 105 100 95 1.0 0.5 90 1 FREQUENCY (MHz) 10 08341-030 85 0.1 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB 0 0.1 1 10 FREQUENCY (MHz) 100 Figure 11. Input Impedance RIN vs. Frequency, 100 Active Termination Figure 14. Output Impedance vs. Frequency Rev. 0 | Page 8 of 28 08341-032 0.1 0.1 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB AD8432 100 1.00 INPUT VOLTAGE NOISE (nV/Hz) 0.95 OUTPUT IMPEDANCE (k) 10 0.90 0.85 1 0.80 0.75 08341-034 1 10 FREQUENCY (MHz) 100 -30 -10 10 30 50 70 90 TEMPERATURE (C) Figure 15. Output Impedance vs. Frequency in Disable Mode 10 16 14 12 Figure 18. Input Voltage Noise vs. Temperature INPUT-REFERRED VOLTAGE NOISE (nV/Hz) f = 1MHz OUTPUT VOLTAGE NOISE (nV/Hz) G = 24.08dB G = 21.58dB 10 8 G = 18.06dB 6 4 2 -50 1 RS THERMAL NOISE ALONE G = 12.04dB 08341-036 1 10 100 1000 -30 -10 10 30 50 70 90 SOURCE RESISTANCE () TEMPERATURE (C) Figure 16. Input-Referred Voltage Noise vs. Source Resistance (RS) 100 Figure 19. Output Voltage Noise vs. Temperature 1.6 OUTPUT-REFERRED VOLTAGE NOISE (nV/Hz) f = 1MHz 1.4 INPUT VOLTAGE NOISE (nV/Hz) 1.2 1.0 0.8 0.6 0.4 0.2 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB G = 24.08dB 10 G = 21.58dB G = 18.06dB G = 12.04dB 08341-035 1 10 100 1000 0.1 1 FREQUENCY (MHz) 10 100 SOURCE RESISTANCE () Figure 17. Output-Referred Voltage Noise vs. Source Resistance (RS) Figure 20. Input Voltage Noise vs. Frequency Rev. 0 | Page 9 of 28 08341-221 1 0 0.01 08341-038 0.1 08341-037 0.1 0.1 0.70 -50 AD8432 20 18 OUTPUT VOLTAGE NOISE (nV/Hz) -40 16 14 12 10 8 6 4 G G G G = 24.08dB = 21.58dB = 18.06dB = 12.04dB -50 -60 DISTORTION (dBc) -70 -80 -90 -100 HD2, 10MHz HD2, 1MHz HD3, 10MHz HD3, 1MHz MEASUREMENT LIMIT 2 08341-222 0.1 1 FREQUENCY (MHz) 10 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOUT (V p-p) Figure 21. Output Voltage Noise vs. Frequency 0 -10 -20 Figure 24. Harmonic Distortion vs. Differential Output Voltage, G = 12.04 dB -40 -50 -60 LOW TONE HIGH TONE IMD3 (dBc) -40 -50 -60 -70 -80 DISTORTION (dBc) -30 -70 -80 HD2, 10MHz HD2, 1MHz HD3, 10MHz HD3, 1MHz MEASUREMENT LIMIT -90 -100 -90 08341-223 -100 1 10 FREQUENCY (MHz) 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOUT (V p-p) Figure 22. IMD3 vs. Frequency 50 45 40 Figure 25. Harmonic Distortion vs. Differential Output Voltage, G = 24.08 dB -50 G = 24.08dB G = 12.04dB -60 DISTORTION (dBc) 35 -70 OIP3 (dBm) 30 25 20 15 10 5 1 10 FREQUENCY (MHz) 100 08341-224 -80 HD2, HD2, HD3, HD3, 10MHz, 10MHz, 10MHz, 10MHz, 2V p-p 1V p-p 2V p-p 1V p-p HD2, HD2, HD3, HD3, 1MHz, 1MHz, 1MHz, 1MHz, 1V p-p 2V p-p 2V p-p 1V p-p -90 -100 -110 0 5 10 CL (pF) 15 20 25 Figure 23. Output Third-Output Intercept vs. Frequency Figure 26. Harmonic Distortion vs. Capacitive Load (CL), G = 12.04 dB Rev. 0 | Page 10 of 28 08341-227 0 08341-226 -110 08341-225 0 0.01 -110 AD8432 -40 -50 -60 -50 HD2, 10MHz, 2V p-p HD2, 1MHz, 2V p-p HD2, 10MHz, 1V p-p -60 DISTORTION (dBc) DISTORTION (dBc) -70 -80 -90 -100 -110 -120 0 5 HD2, HD2, HD3, HD3, 10 10MHz, 10MHz, 10MHz, 10MHz, 15 2V p-p 1V p-p 2V p-p 1V p-p 20 HD2, HD2, HD3, HD3, 25 1MHz, 1MHz, 1MHz, 1MHz, 1V p-p 2V p-p 2V p-p 1V p-p 08341-228 -70 HD3, 10MHz, 2V p-p HD2, 1MHz, 1V p-p -80 HD3, 10MHz, 1V p-p -90 HD3, 1MHz, 2V p-p -100 HD3, 1MHz, 1V p-p 30 35 2 4 6 8 10 GAIN (V/V) 12 14 16 18 CL (pF) Figure 27. Harmonic Distortion vs. Capacitive Load (CL), G = 24.08 dB -50 -55 -60 DISTORTION (dBc) -70 -75 -80 -85 Figure 30. Harmonic Distortion vs. Gain CROSSTALK (dB) -65 -70 -75 -80 -85 -90 08341-229 -90 -95 -100 -105 -110 -115 1 10 100 08341-232 HD2, HD2, HD3, HD3, 10MHz, 10MHz, 10MHz, 10MHz, 2V p-p 1V p-p 2V p-p 1V p-p HD2, HD2, HD3, HD3, 1MHz, 1MHz, 1MHz, 1MHz, 1V p-p 2V p-p 2V p-p 1V p-p -95 0 200 400 600 800 1000 1200 1400 1600 1800 2000 RL () -120 0.1 FREQUENCY (MHz) Figure 28. Harmonic Distortion vs. Resistive Load (RL), G = 12.04 dB -50 -55 -60 Figure 31. Channel Crosstalk vs. Frequency DISTORTION (dBc) -65 -70 -75 -80 -85 -90 -95 0 200 400 1V/DIV HD2, HD2, HD3, HD3, 10MHz, 10MHz, 10MHz, 10MHz, 2V p-p 1V p-p 2V p-p 1V p-p HD2, HD2, HD3, HD3, 1MHz, 1MHz, 1MHz, 1MHz, 1V p-p 2V p-p 2V p-p 1V p-p 600 800 1000 1200 1400 1600 1800 2000 RL () Figure 29. Harmonic Distortion vs. Resistive Load (RL), G = 24.08 dB 08341-230 100ns/DIV Figure 32. Overdrive Recovery, G = 12.04 dB Rev. 0 | Page 11 of 28 08341-132 08341-231 -110 AD8432 CL = 15pF CL = 10pF CL = 5pF 50mV/DIV 1V/DIV 100ns/DIV 08341-013 10ns/DIV Figure 33. Overdrive Recovery, G = 24.08 dB Figure 36. Small Signal Transient Response vs. Capacitive Load (CL), G = 12.04 dB G = 24.08dB CL = 5pF CL = 10pF CL = 15pF CL = 20pF CL = 30pF G = 21.58dB 200mV/DIV G = 18.06dB G = 12.04dB 50mV/DIV 08341-014 10ns/DIV 10ns/DIV Figure 34. Small Signal Transient Response vs. Gain, VIN = 100 mV p-p Figure 37. Small Signal Transient Response vs. Capacitive Load (CL), G = 24.08 dB RL = 499 RL = 249 RL = 24.9 RL = 15 RL = 10 100mV/DIV 50mV/DIV 08341-015 10ns/DIV 10ns/DIV Figure 35. Small Signal Transient Response, G = 12.04 dB Figure 38. Small Signal Transient Response vs. Resistive Load (RL), G = 12.04 dB Rev. 0 | Page 12 of 28 08341-018 08341-017 08341-016 AD8432 RL = 499 RL = 249 RL = 24.9 RL = 15 RL = 10 CL CL CL CL = 20pF = 15pF = 10pF = 5pF 08341-019 500mV/DIV 50mV/DIV 10ns/DIV 10ns/DIV Figure 39. Small Signal Transient Response vs. Resistive Load (RL), G = 24.08 dB Figure 42. Large Signal Transient Response vs. Capacitive Load (CL), G = 12.04 dB G = 12.04dB G = 18.06dB G = 21.58dB G = 24.08dB CL CL CL CL CL = 30pF = 20pF = 15pF = 10pF = 5pF 08341-020 500mV/DIV 50mV/DIV 10ns/DIV 10ns/DIV Figure 40. Small Signal Transient Response vs. Gain, VOUT = 200 mV p-p Figure 43. Large Signal Transient Response vs. Capacitive Load (CL), G = 24.08 dB G = 24.08dB RL = 499 RL = 249 RL = 24.9 RL = 15 G = 21.58dB 500mV/DIV 500mV/DIV G = 18.06dB G = 12.04dB 08341-021 10ns/DIV 10ns/DIV Figure 41. Large Signal Transient Response vs. Gain, VIN = 125 mV p-p Figure 44. Large Signal Transient Response vs. Resistive Load (RL), G = 12.04 dB Rev. 0 | Page 13 of 28 08341-024 08341-023 08341-022 AD8432 RL RL RL RL RL = 499 = 249 = 24.9 = 15 = 10 SUPPLY CURRENT (mA) 08341-025 30 28 500mV/DIV 26 24 22 10ns/DIV -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 45. Large Signal Transient Response vs. Resistive Load (RL), G = 24.08 dB 140 120 SUPPLY CURRENT (A) Figure 48. Supply Current vs. Temperature G = 12.04dB G = 18.06dB G = 21.58dB G = 24.08dB 100 80 60 40 20 500mV/DIV 08341-026 10ns/DIV -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 46. Large Signal Transient Response vs. Gain, VOUT = 2 V p-p -20 -30 -40 -50 -60 -70 -80 -90 -100 0.01 G = 24.08dB NO BYPASS CAPS Figure 49. Supply Current vs. Temperature in Disable Mode PSRR (dB) 0.1 1 10 100 FREQUENCY (MHz) Figure 47. PSRR vs. Frequency 08341-248 Rev. 0 | Page 14 of 28 08341-028 0 -60 08341-027 20 -60 AD8432 ENB 5V/DIV 1 1 ENB 5V/DIV OUTPUT 50mV/DIV 2 2 OUTPUT 500mV/DIV 08341-252 TIME (100s/DIV) TIME (100s/DIV) Figure 50. Small Signal Enable Response Figure 51. Large Signal Enable Response Rev. 0 | Page 15 of 28 08341-251 AD8432 TEST CIRCUITS RFB 1MHz (10MHz LPF) 0.1F INH OPL RSH 1MHz (10MHz) CSH INL 0.1F 0.1F INH RL INL 475 56.2 LP 1.7MHz (10.7MHz) 50 08341-046 0.1F SPECTRUM ANALZYER DUAL FILTER HP 50 AD8432 LNA1 0.1F AD8130 G=1 RL Figure 52. Harmonic Distortion vs. Resistive Load (RL) Measurements RFB 1MHz (10MHz LPF) 0.1F INH INL 0.1F CSH 0.1F DUAL FILTER LP 50 0.1F 487 0.1F 08341-049 SPECTRUM ANALYZER IN 50 OPL OPH 487 26.1 1:1 HP 1.7MHz (10.7MHz) RSH 1MHz (10MHz) CL AD8432 LNA1 26.1 RL CL Figure 53. Harmonic Distortion vs. Capacitive Load (CL) Measurements NETWORK ANALYZER OUT 50 50 IN RFB 0.1F 499 5pF 0.1F INH INL OPL OPH 0.1F DIFF PROBE RSH CSH AD8432 0.1F LNA1 0.1F 499 5pF 08341-047 08341-048 Figure 54. Frequency Response Measurements SPECTRUM ANALYZER 0.1F INH INL 0.1F OPL 0.1F 1k OPH 50 AD8432 LNA1 0.1F 1k AD8129 G = 10 Figure 55. Voltage Noise Measurements Rev. 0 | Page 16 of 28 AD8432 5pF RFB 10MHz X MULTIPLIER Y RSH CSH 1MHz INL 0.1F INH 0.1F 499 DIFF PROBE OSCILLOSCOPE CH1 0.1F AD8432 0.1F LNA1 0.1F 499 5pF 08341-050 Figure 56. Overdrive Recovery Measurements 499 NETWORK ANALYZER 50 RFB 0.1F 5pF OUT RSH CSH 0.1F INH INL 0.1F OPL OPH 0.1F 0.1F AD8432 LNA1 499 5pF 08341-051 Figure 57. Input Impedance vs. Frequency Measurements RFB 0.1F NETWORK ANALYZER 0.1F 0.1F 499 08341-052 0.1F RSH CSH INH INL 0.1F OPL OPH 50 AD8130 LNA1 Figure 58. Output Impedance vs. Frequency Measurements RFB 0.1F SPECTRUM ANALYZER 0.1F RS INH1 OPL1 0.1F 1k +IN OUT -IN 08341-054 50 OPH1 INL1 0.1F AD8432 LNA1 0.1F 1k AD8129 G = 10 Figure 59. Noise Figure Measurements Rev. 0 | Page 17 of 28 AD8432 THEORY OF OPERATION LOW NOISE AMPLIFIER (LNA) The AD8432 is a dual-channel, ultralow noise amplifier with integrated pin-strappable, gain-setting resistors. The resistors can be externally connected to achieve differential gains of 12.04 dB, 18.06 dB, 21.58 dB, and 24.08 dB (x4, x8, x12, and x16). A simplified schematic of a LNA is shown in Figure 60. The LNA is driven with a single-ended input and measured differentially at the output. The inverting input INL must be ac-coupled to ground through a capacitor for proper operation. The LNA cannot be driven differentially due to the asymmetry of the internal gain setting resistors. The gain from the inverting input INL to the single-ended output (OPH or OPL) does not match the gain from the noninverting input INH to the singleended output. The AD8432 inputs have a dc bias voltage of 3.25 V, which is generated internally. The inputs must be ac-coupled through a series capacitor to maintain the dc bias level of the inputs. Likewise, the AD8432 outputs have a dc bias voltage of 2.5V. An ac coupling capacitor in series with each connection is recommended to prevent improper loading of the outputs. The AD8432 supports a differential output voltage of 4.8 V p-p for the common-mode output voltage of 2.5 V. Therefore, for a differential gain G = 12.04 dB, the maximum input voltage allowed is 1.2 V p-p. RFB VPS Clamping the inputs ensures quick recovery from large input voltages. The input back-to-back diodes, which are integrated inside the die (IND1 and IND2), should be used for the lowest gain configuration (12.04 dB) to protect the input from overdriving. They should be connected after the source resistance or before the INH coupling capacitor. The use of a fully differential topology and negative feedback minimizes distortion. A differential signal enables smaller swings at each output, which results in reduction of third-order distortion. The AD8432 is a voltage feedback amplifier. Due to gain bandwidth product (GBW), a decrease in bandwidth should be expected as the gain increases. Table 5 displays the values of -3 dB bandwidth for each gain with unterminated input impedance. GAIN SETTING TECHNIQUE Pin strapping is used to set the gain of the amplifier. Gain setting resistors are integrated in the LNA and are accessible externally through the GOH, GMH, GML, and GOL pins. By externally shorting these pins, and thereby shorting or connecting the internal resistors, the AD8432 can be configured for four different gains. Table 5 shows which pins must be connected to achieve the desired gain. CFB I I OPH OPL INL Q1 CINH RSH INH CSH RS GND VS 08341-039 Q2 RG1 12 RG5 24 I RG6 24 RG7 48 CINL RG4 48 RG3 24 RG2 12 I GND GML GOL GOH GMH GND Figure 60. Simplified Schematic of LNA Table 5. Gain Setting Using Pin-Strapping Technique and -3 dB Bandwidth for Each Gain Configuration Differential Gain (dB) 12.04 18.06 21.58 24.08 Single Gain (dB) 6.02 12.04 15.56 18.06 -3 dB BW (MHz) 200 90 50 32 RG1 () 12 12 12 12 RG2 () 12 12 12 12 RG3 () Connect GMH to GOH 24 Connect GMH to GOH 24 Rev. 0 | Page 18 of 28 RG4 () Connect GOH to OPH Connect GOH to OPH 48 48 RG5 () 24 24 24 24 RG6 () Connect GML to GOL 24 Connect GML to GOL 24 RG7 () Connect GOL to OPL Connect GOL to OPL 48 48 AD8432 The single-ended gain from INH to OPH (see Figure 60) is defined as G OPH - INH = RG1 + RG2 + RG3 + RG4 RG1 RG5 + RG6 + RG7 RG1 To achieve this active impedance match, connect a feedback resistor RFB between the INH and OPL (see Figure 61). RIN is given in Equation 1, where G/2 is the single-ended gain. R IN = The single-ended gain from INH to OPL is defined as R FB G 1+ 2 (1) G OPL - INH = - The values of the seven gain resistors were chosen so that both single-ended gains are equal. For example, to set a gain of 12.04 dB (G = x4) differentially, the gain from INH to each output (OPH, OPL) should be 6.02 dB (G = x2). INH to OPH: For RG1 = RG2 = RG, then In addition, to further reduce the input resistance, there is an internal resistance of 6.2 k in parallel with the source resistance, such that R IN = R FB R G INTERNAL 1+ 2 (2) G OPH - INH = RG1 + RG2 2 x RG = =2 RG1 RG Equation 3 should be used to calculate RFB accurately for a desired input resistance and single-ended gain. Refer to Table 6 for calculated results for RFB for several input resistance and gain combinations. INH to OPL: For RG1 = RG and RG5 = 2 x RG, then G OPL - INH 2 x RG R = - G5 = - = -2 RG1 RG R FB ACTIVE INPUT RESISTANCE MATCHING The AD8432 reduces noise and optimizes signal power transfer by using active input termination to perform signal source resistance matching. The primary purpose of input impedance matching is to optimize the input signal power transfer. With resistive termination, the input noise increases due to the thermal noise of the terminating resistor and the increased contribution of the input voltage noise generator of the LNA. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + 1/2LNA Gain). The noise figure (NF) for the three terminating schemes are shown in Figure 62. RIN RS VIN UNTERMINATED RIN RS VIN INH LNA RS RESISTIVE TERMINATION RFB RIN RS VIN ACTIVE IMPEDANCE MATCH INH LNA VOUT 4 08341-009 G R IN 1 + 2 = , R INTERNAL = 6.2 k R IN 1- R INTERNAL (3) 8 7 6 NOISE FIGURE (dB) 5 4 3 2 1 RESISTIVE TERMINATION (RS = RIN) ACTIVE IMPEDANCE MATCH UNTERMINATED (SIMULATED RESULTS) 100 RS () 1000 08341-267 0 50 INH LNA VOUT Figure 62. Noise Figure vs. RS for Resistive, Active Match, and Unterminated Inputs 18 16 VOUT NOISE FIGURE (dB) 14 12 10 8 6 RIN = 1k RIN = 200 RIN = 100 RIN = 75 RIN = 50 RIN = UNTERMINATED 2 (SIMULATED RESULTS) 100 RS () 1k 08341-268 Figure 61. Input Resistance Matching 0 50 Figure 63. Noise Figure vs. RS for Various Values of RIN, Actively Matched Rev. 0 | Page 19 of 28 AD8432 The user must determine the level of matching accuracy desired and adjust RFB accordingly. The RFB and CFB network presents a load to OPL that OPH does not see. The user may add an identical load on OPH, to improve slightly the distortion caused by this imbalance. There is a feedback capacitor (CFB) in series with RFB (see Figure 60) because the dc levels of the positive output and the positive input are different. At higher frequencies, the value of the feedback capacitor needs to be considered. Table 6. Feedback Resistance for Several RIN and Gain Combinations Desired RIN () 50 75 100 200 1k 50 100 50 100 50 100 Differential Gain (V/V) 4 4 4 4 4 8 8 12 12 16 16 Single-Ended Gain, G/2 (V/V) 2 2 2 2 2 4 4 6 6 8 8 Exact RFB (), Equation 2 151.2 227.8 304.9 620 3.58 k 252 508.2 352.9 711.5 453.7 914.8 RFB (), 1% Standard Value 150 226 301 619 3.57 k 250 511 357 715 453 909 Actual RIN (), Equation 2 49.6 74.4 98.7 199.7 998.4 49.6 100.5 50.6 100.5 49.9 99.4 The unterminated bandwidth (RFB = ) is 200 MHz. The AD8432 has a low input referred voltage noise of 0.85 nV/Hz at the lowest gain, 12.04 dB (unterminated configuration). To achieve such low noise, the dual amplifier consumes 24 mA, resulting in a power consumption of 120 mW. Rev. 0 | Page 20 of 28 AD8432 APPLICATIONS INFORMATION The AD8432 LNA provides precision gain and ultralow noise performance with minimal external components. Because it is a high performance part, care must be taken to ensure that it is configured optimally to attain the best performance and dynamic range for the system. The unterminated input impedance of the AD8432 is 6.2 k. Any input resistance between 50 and 6.2 k can be synthesized using active impedance matching. At the lowest gain (12.04 dB), the gain response exhibits some peaking at higher frequencies. An RC shunt network at the input (see RSHx and CSHx in Figure 64) is recommended to reduce gain peaking and enhance stability at higher frequencies. Table 7 shows the recommended values of RFB, CSH, and RSH for all four gains and several input impedance combinations. The values for the CSH and RSH network are determined empirically and can be customized as needed to optimize performance. As RIN increases, the value of CSH diminishes, and for higher input impedance values, no capacitor may be required. TYPICAL SETUP The internal bias circuitry of the AD8432 sets the input bias voltage at 3.25 V and the output bias voltage at 2.5 V. It is important to ac-couple the inputs through a capacitor to maintain the internal dc bias levels. When active input termination is used (RFB), a decoupling capacitor (CFB) is required to isolate the input and output bias voltages of the LNA. A typical value for CFB is 0.1 F, but a smaller value capacitor is more appropriate at higher frequencies. RFB1 CFB1 0.1F FB 120nH G = 12dB 0.1F 0.1F ENB VPS1 VPS2 COMM BIAS FB 120nH IN1 RSH1 15 CSH1 47pF 0.1F INH1 IND1 LNA1 OPH1 OPL1 GMH1 GOH1 GOL1 GML1 RL 0.1F OUT1+ CL OUT1- 0.1F INL1 0.1F FB 120nH IN2 RSH2 15 CSH2 47pF 0.1F INH2 IND2 LNA2 OPH2 OPL2 GMH2 GOH2 GOL2 GML2 RL 0.1F OUT2+ CL OUT2- 0.1F INL2 0.1F AD8432 RFB2 CFB2 0.1F 08341-040 Figure 64. Typical AD8432 Setup, G = 12.04 dB Rev. 0 | Page 21 of 28 AD8432 Table 7. External Components Selections for Common Input Impedance RIN () 50 Gain (dB) 12 18 21 24 12 18 21 24 12 18 21 24 12 18 21 24 12 18 21 24 12 18 21 24 12 18 21 24 RFB () 150 249 357 453 226 383 536 681 301 511 715 909 619 1.02 k 1.43 k 1.87 k 3.57 k 5.9 k 8.25 k 10.7 k CSH (pF) 47 30 None None 36 None None None 30 None None None 18 None None None 10 None None None None None None None None None None None RSH () 15 15 None None 15 None None None 15 None None None 15 None None None 10 None None None None None None None None None None None -3 dB BW (MHz) 176 116 117 87 167 144 100 72 164 134 90 63 164 116 74 51 160 99 61 43 178 95 59 40 210 96 55 38 75 100 200 1k Unterminated, RS = 50 Unterminated, RS = 0 Rev. 0 | Page 22 of 28 AD8432 I/Q DEMODULATION FRONT END The AD8432 low noise amplifiers can be used to drive the differential RF inputs of the dual AD8333 or the quad AD8339 I/Q demodulators. The primary application for the AD8339 is phased array beamforming in medical ultrasound, specifically in CW Doppler processing. Other applications include phased array radar and smart antennas for mobile communications. AD8021 Q1 0.1F 20 RF1P Q1OP resistors. The 4LOP and 4LON pins of the AD8339 are driven by a differential clock signal, which has a frequency 4x that of the RF inputs. The AD8339 downconverts the RF signals, generates quadrature, and phase-shifts the resultant I and Q signals. The I and Q outputs of the AD8339 are current outputs. A transimpedance amplifier, such as the AD8021, processes the outputs and performs several functions, including the following: * * * 787 2.2nF 2.2nF 787 Current-to-voltage conversion Summation amplifier for multiple channels Active low-pass filter AD8432 20 0.1F AD8339 RF1N 4LOP 0.1F I1OP I1 AD8021 Figure 65. Block Diagram of AD8432 + AD8339 Application for Ultrasound Beamforming In beamforming applications, the I and Q outputs of a number of receiver channels are summed, which increases the system dynamic range by 10 log10 (N), N being the number of channels being summed. The external RC feedback network of the AD8021 is a 100 kHz low-pass filter as shown in Figure 65. Refer to the AD8333 and AD8339 datasheets for more details on implementing I/Q demodulators. Evaluation boards are available for the AD8432 and the AD8339 to facilitate system level design and test. A detailed reference schematic of the setup is shown in Figure 66. The AD8432 is shown in this configuration with a gain of 12.04 dB, with unterminated inputs. If active termination is preferred, use an RFB and CFB network as discussed in the Theory of Operation. Clamping diodes IND1/IND2 can be connected to IN1/IN2 to protect the LNA input from being overdriven. Because of its low output noise and low distortion, the AD8432 ensures minimal degradation in dynamic range while amplifying the RF input signal. At the lowest gain of 12.04 dB, the AD8432 contributes only 3.4 nV/Hz output voltage noise. Figure 65 shows a simplified block diagram of one channel of the AD8432 driving the AD8339. The AD8432 outputs can be connected directly to the AD8339 RF inputs through 20 08341-041 4LO 0.1F 0.1F ENB IN1 +5V 0.1F 0.1F VPOS -5V 0.1F VNEG 4LOP +5V 787 2.2nF 27 - VPS1 VPS2 BIAS COMM 0.1F RSH1 15 CSH1 47pF INH1 IND1 LNA1 GMH1 GOH1 GOL1 GML1 OPH1 OPL1 20 RF1P 20 RF1N Q1OP I1OP AD8021 + 34 6 0 Q1 + Q2 0.1F -5V +5V OPH2 20 RF2P 20 RF2N Q2OP 0.1F I2OP 27 - INL1 IN2 0.1F INH2 RSH2 0.1F 15 CSH2 47pF 0.1F IND2 LNA2 787 2.2nF OPL2 GMH2 GOH2 GOL2 GML2 INL2 AD8339 G = -1.3dB AD8021 + 34 6 0 I1 + I2 G = 12dB LPF fC = 100kHz 0.1F -5V Figure 66. Schematic of AD8432 (G = 12.04 dB) + AD8339 Application for Ultrasound Beamforming Rev. 0 | Page 23 of 28 08341-043 AD8432 AD8432 DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION Some applications require the low noise and high dynamic range of the AD8432; however, they may also require a singleended output, rather than a differential output. The AD8129 and AD8130 differential receiver amplifier can be used for the differential-to-single-ended conversion of the AD8432 output, as shown in Figure 67. The AD8129 is a low noise, high gain (10 or greater) amplifier intended for applications over very long cables, where signal attenuation is significant. The AD8130 is stable at a gain of 1 and can be used for applications where lower gains are required. The AD8129 and AD8130 have user-adjustable gain, set by the ratio of two resistors, to help compensate for losses in the transmission line. A transformer or balun can also be used to convert the differential output of the AD8432 to a single-ended output. Transformers have lower distortion; however, care must be taken to properly match the impedance of the transformer. The test circuit for distortion measurements in Figure 53 uses an ADTT1-1 transformer to perform differential-to-single-ended conversion. 0.1F 0.1F ENB IN1 VPS1 VPS2 BIAS COMM SERIES R IF DRIVING HIGH CAP LOAD OPH1 20 20 AC-COUPLING CAPS (AD8432 HAS 2.5V OUTPUT BIAS) +VS 0.1F RSH1 15 CSH1 47pF 0.1F INH1 IND1 0.1F 0.1F 499 499 LNA1 GMH1 GOH1 GOL1 GML1 OPL1 1 8 4 5 + - + - 7 6 2 VOUT1 INL1 AD8130 R'S PROVIDE BIAS CURRENT PATH AND TERMINATION IF NECESSARY 08341-044 G = 12 dB -VS Figure 67. AD8432 Differential-to-Single-Ended Conversion Using the AD8129/AD8130 with Unity Gain Rev. 0 | Page 24 of 28 AD8432 EVALUATION BOARD Figure 68 shows the AD8432 evaluation board, and the schematic diagram is shown in Figure 69. Using the board is a convenient and fast way to verify system design and assess the performance of the AD8432 under the user-specific operating conditions. The board provides access to all LNA inputs, outputs, and gain setting pins. The board is shipped in a typical G = 12.04 dB configuration but is designed to allow customization of the setup as required. The AD8432-EVALZ requires a single 5 V power supply. An on-board switch (S1) allows VPS to drive the enable (ENB) input. Table 8 outlines which resistors or headers need to be installed or shorted for each gain configuration. Table 8. Gain Setting Using Resistors or Headers LNA1 W5 W6 W7 W8 LNA2 R9 W9 R10 W10 R11 W11 R12 W12 4 X1 X1 X1 X1 Gain (V/V) 8 12 X1 X1 X1 X1 16 R1 R2 R3 R4 1 GAIN SETTING Headers (W5 to W12) are provided across the gain setting pins and can be shorted using jumpers to allow gain setting quickly and easily. Alternately, it is recommended to short the gain setting pins using surface-mount (0402), 0 resistors (R1 to R4, R9 to R12) that eliminate the small parasitic capacitances from longer trace lengths to the headers. As shipped, the evaluation board is configured for G = 12.04 dB with these 0 resistors. X = shorting the indicated header or resistor. Figure 68. Evaluation Board Rev. 0 | Page 25 of 28 08341-045 AD8432 SCHEMATIC BANANA JACK VPOS VPOS W3 TEST POINT GND AD8432 EVAL BOARD SCHEMATIC BANANA GND JACK RFB1 DNI L3 120nH FB +5V ENABLE DISABLE S1 PRB3 GOL1 18 GOL1 CFB1 0.1F DNI OPH1 GND1 GND2 GND3 VPS1 W7 R3 0 RL1 DNI CL1 DNI R5 DNI C9 0.1F DNI C3 ENB 0.1F R1 0 R2 0 GOH1 GMH1 W5 W6 GML1 R7 453 DNI OPH1 GMH1 20 GOH1 21 GML1 19 OPH1 22 VPS1 23 ENB 24 L1 IN1 120nH FB RSH1 15 INL1 W8 R6 DNI INL1 2 17 OPL1 IND1 3 16 COM1 COMM 4 15 COM2 INH1 1 C5 PIN 1 0.1F INH1 IDENTIFIER R4 0 OPL1 COM1 OPL2 R14 DNI RL4 DNI C8 0.1F DNI RL2 DNI C7 0.1F DNI T1 4 2 6 R17 0 VOUT1 3 DNI CL2 C10 DNI 0.1F DNI 1 PRB1 CSH1 47pF C1 0.1F TOP VIEW (Not to Scale) 14 OPL2 13 GOL2 OPL1 W1 COMM INL2 INL2 5 AD8432 R8 453 DNI C14 0.1F DNI R16 453 DNI OPL2 W4 VPOS 08341-042 Figure 69. Schematic C2 0.1F INH2 INH2 6 Rev. 0 | Page 26 of 28 PIN 0 EXPOSED PADDLE (TIED TO GND) R12 0 GOL2 W12 L2 IN2 120nH FB PRB2 C6 0.1F 12 GML2 11 GMH2 10 GOH2 7 IND2 8 VPS2 9 OPH2 PRB4 C12 0.1F DNI C11 0.1F DNI CL4 DNI CL3 C13 DNI 0.1F DNI RL3 DNI T2 4 2 6 RSH2 15 CSH2 47pF R9 R10 0 0 R11 0 R18 0 VOUT2 3 DNI 1 W2 C4 0.1F VPS2 L4 CFB2 0.1F 120nH FB DNI OPH2 R13 DNI GML2 W11 W9 W10 GOH2 GMH2 GND4 GND5 GND6 R15 453 DNI OPH2 RFB2 DNI AD8432 POWER SUPPLY The AD8432 should be powered by a single 5 V supply connected to the VPOS terminal. Separate supplies can be used for VPS1, VPS2, and ENB, or they can all be tied to VPOS by shorting the W3 and W4 headers and the S1 switch. Ferrite beads and decoupling capacitors are installed for isolation, protection, and power supply noise reduction. OUTPUT The AD8432 evaluation board provides the space to configure the output loading conditions required by the user, by populating the given footprints (for example, RL1, RL2, C7, and C8). SMA connectors are available at the outputs, and space for a transformer is also available for differential-to-single-ended conversion. The 4-pin headers, PRB3 and PRB4, are placed close to the AD8432, and they provide a way for monitoring the differential output or the single-ended output using a high impedance differential probe. The two inner pins of the headers are connected to OPL/OPH, and the two outer pins of the headers are connected to ground. There are several footprints provided to install ac coupling capacitors at the outputs (C7 to C14). The AD8432 outputs are biased internally at 2.5 V. To maintain the dc bias level, use coupling capacitors between the outputs and the load. INPUT TERMINATION Active input impedance matching can be realized by installing a feedback resistor (RFB), the value of which is determined by the gain and source impedance, as described in the Theory of Operation section. CFB provides the necessary ac coupling between the input and output when using active termination; a 0.1 F capacitor value is recommended. The RFB and CFB network presents a load to OPL, and an equivalent load at OPH can be used to balance the differential output. Input clamping diodes (IND1 and IND2) can be connected to the inputs, by shorting the connection on the W1 and W2 headers. The diodes provide overvoltage protection to the input and enable faster overdrive recovery times, especially at the lowest gain (12.04 dB). Rev. 0 | Page 27 of 28 AD8432 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.50 BSC 0.30 0.25 0.18 19 18 EXPOSED PAD 24 1 PIN 1 INDICATOR 2.65 2.50 SQ 2.45 6 7 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 13 12 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. Figure 70. 24-Lead Lead Frame Chip Scale Package [LFSCP_WQ] 4 mm x 4 mm, Very Very Thin Quad (CP-24-7) Dimensions shown in millimeters ORDERING GUIDE Model AD8432ACPZ-R7 1 AD8432ACPZ-RL1 AD8432ACPZ-WP1 AD8432-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 24-Lead LFCSP_WQ, 7" Tape and Reel 24-Lead LFCSP_WQ, 13" Tape and Reel 24-Lead LFCSP_WQ, Waffle Pack Evaluation Board 112108-A Package Option CP-24-7 CP-24-7 CP-24-7 Z = RoHS Compliant Part. (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08341-0-10/09(0) Rev. 0 | Page 28 of 28 |
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